    wire               clk_50m, clk_100m;
    wire               locked;

 (*mark_debug="true"*)  reg [31:0]         pma_init_cnt;
 (*mark_debug="true"*)  reg                pma_init_r;
 (*mark_debug="true"*)  reg                pma_reset_r;
   
   always @ ( posedge clk_50m or negedge locked ) begin
      if(!locked)begin
         pma_init_cnt <= 0;
         pma_init_r <= 1;
         pma_reset_r <= 1;
         
         
      end
      else begin
         if(pma_init_cnt != 67108863 )begin
            pma_init_cnt <= pma_init_cnt + 1;
                        
         end
         
         if(pma_init_cnt == 1)begin
            pma_init_r <= 0;
            
            pma_reset_r <= 1;
         end
         else if(pma_init_cnt == 50)begin
            pma_init_r <= 1;
            pma_reset_r <= 1;

         end
         else if(pma_init_cnt == 60000000  )begin
            pma_init_r <= 0;
            pma_reset_r <= 1;
         end
         else if(pma_init_cnt == 67108860 )begin
            pma_init_r <= 0;
            pma_reset_r <= 0;
         end
        
         
      end
   end // always @ ( posedge clk_50m or negedge locked )

  
   

   clk_wiz_0 clk_pll
     (
      // Clock out ports
      .clk_out1( clk_50m),     // output clk_out1
      .clk_out2( clk_100m),     // output clk_out2
      // Status and control signals
      
      .locked(locked),       // output locked
      // Clock in ports
      .clk_in1(clk_in1));      // input clk_in1
